Responsible for new customer technology promotion and engage supportSuccessfullycollaborate engage BCD/HV customers and MP Successfullycollaborate engage SOI/SiGe/GaAs customers and MPSuccessfully collaborate engage of advanced technology node(65nm/40nm/28nm/16nm) customers and MP and E.S.(12nm)Responsible for investigation and management of foundry technologyFinish leading foundries advanced technology(16nm/12nm..) and special technology (BCD/HV/CIS)product spec required benchmarkCoordinate customers requested technology development and related PDK/Lib delivery and management from multi-foundryResponsible for design and porting foundry technical supportSupport setup 3DIC WoW technology design reference flowSuccessfully support setup 16nm/12nm/7nm advanced technology design infrastructureSuccessfully finish MEMS/power MOSFET customized technology porting at foundry Successfully finish HV technology porting and MP for DDI customers Successfully finish SiC MOSFET technology porting and T.O. for automotive customers

Responsible for tape out service and reviewComprehensive leading foundries T.O. success records from logic platform 0.35um~65nm/40nm/28nm~16nm/12nm (E.S. now)Comprehensive leading foundries T.O. success records of BCD/HV... special technologyResponsible for Product process optimization supportSuccessfully support key BCD customers develop and implement depletion MOS/Zener diode/HR/Capacitor to get more MP Optimize foundry HV technology so as to extend SD MP windowOptimize customized MEMS technology so as to speedup T.O. scheduleOptimize customer used devices to enhance Bin1 rate and satisfaction Successfully develop and optimize foundry BCD devices(depletion MOS/Zener diode/HR/Capacitor) to get more MPResponsible for product yield improvement and maintenance Enlarge device window for MP and keep CP yield D0<0.05 of 28nm SoC product designed with few process marginSuccessfully improve leading DDI customers’ SD product to 96%Optimize foundry BCD RS_P+ variation so as to let product CP from unstable(0~90%) to stable 99%Cycle time reduced Improve and maintain major handled MP product CP record (65nm/40nm/28nm..) D0 <0.05Cycle time reduced Improve and maintain major handled MP product CP record (BCD/HV/SOI...) D0 <0.05Responsible for product reliability qualificationFinish 65nm/40nm/28nm and RFSiP products reliability qualificationProvided solution to solve customer product eFuse latch-up issueCoordinate (Assembly and Testing department) to provide solution as products reliability qualification failure happened

Responsible for intercap/RF TV design modeling and methodology setupSupport Qualcomm 28nm RF devices test chip vs. model S2S verificationSupport MediaTek 0.11um BEOL LPE RC extraction S2S from matrix of INV/NOR/NAND type oscillator measurementSuccessfully deliver 40nm inter-cap model development Successfullydevelop advanced process inter-cap model Raphael simulation auto-generation environmentEstablish advanced process BB/RF RES/MIM/MOM/CAP/TSV and wire modelsSuccessfully optimize EMX generator environment for OXF models Establish transmission line modeling methodologyImprove advanced process model methodology : cycle time improve max 50%, accuracy improve max 80% by Macro, DOE and STATISTICACollaborate with LPE for advanced process tools accuracy improvement 40nm TML modeling test key design and layoutEstablish TSV coupling capacitance extraction methodologyConsolidate MQA program to enhance model delivery quality14nm inter-cap and resistor modeling test key design and layout Evaluate inter-cap modeling next generation toolsSuccessfully develop customized models for customers

Successfully develop FBEOL 0.13um, 90nm, 65nm, 55nm, 45nm

BOAC( Bonding Over Active Circuit) processBOAC project risk mitigation by stress simulation and nanoindentation

45nm FBEOL(WB,FC) test vehicle development and verification

Ramp up 0.13um BOAC product mass production : (cost down ~30%)Establish 90nm copper pad direct bump technology

Coordinate 90nm GF FBEOL(WB,FC) technology development

Support 0.13um LOGIC technology process qualification include device qualification and product(SRAM) qualification0.13um LOGIC process integration and developmentEstablish test vehicle for soon in-line issue feedback and solvingIntegrate TD and fab task force members for process development

Successfully introduce to mass production for key customers product by effectively yield improvement (D.D.<0.05)Successfully develop half-node process to extend customer’s product lifeConsolidate process : line yield improve 8.5%, LOGIC dual-voltage device life>>10 yearsEffectively reduce in-line process abnormality by root cause solving and process margin optimizationCollaborate with IT on yield improvement tools

0.35um LOGIC SALICIDE process integration and development

Successfully transfer 0.35um LOGIC process to Fab 8AB