⚫ TOF (time of fly) pixel design, platform build up at tsmc
and pixel process integration optimization
and Mass production within 3 silicon run
⚫ FOD (fingerprint on display) pixel design, platform build up at
tsmc , PSMC , SMIC and pixel process integration optimization
and Mass production within 3 silicon run
⚫ FOD Mask Reduction and Mass production
⚫ CMOS image sensor R & D
⚫ Pixel circuit design use Cadence Virtuoso schematic
⚫ Pixel & test-key design by TCAD simulation and laker layout
⚫ Pixel performance characteristic
⚫ Pixel process platform design & development
⚫ Pixel & Optical module R & D
⚫ Familiar with major foundry CIS BSI,FSI process flow

⚫ CMOS image sensor performance WAT & Cp Yield analysis
⚫ Foundry contact window

⚫ Mass Production VGA & 2M cmos image sensor
⚫ CMOS image sensor R & D
⚫ Pixel circuit design
⚫ Pixel performance characteristic
⚫ Pixel process platform design & development
⚫ Familiar with major foundry CIS BSI,FSI process flow
⚫ CMOS image sensor performance WAT & Cp Yield analysis
⚫ Foundry contact window

⚫ RD process integration
⚫ 45nm HKMG gate first research, integration, co-author public paper
⚫ HKMG, raised S/D advanced technology development
⚫ Copper Low-K integration
⚫ Slim spacer development in 65nm node
⚫ 110nm platform cross Fab (Taiwan, Singapore, Shanghai) device tuning
& alignment

⚫ RD Advanced Device Development, including stress technology, HKMG,
⚫ Finfet structure device, SiGe channel device, integrate Cu Low-K
⚫ 90nm, 130nm new process development
⚫ Patent spacer-less advanced scheme
⚫ 2005 iedm publish and present paper at Washington
⚫ Qualified to Austin SEMITEK for HKMG research
⚫ Thin film module, major in PECVD

⚫ Use quantox measure electric property of gate oxide of devices
⚫ Integration with diffusion dept. in order to improve devices quality
⚫ Maintain RTP

⚫ Experiment plan and integration

⚫ New technical process development with Ericsson for
Blue tooth project
⚫ THICK FILM process development