负责管理器件开发部,包括Logic器件, SRAM,TCAD, WAT等部门。负责器件技术规划和开发,团队管理,人员招募,技术培训等。

一:16nm Finfet 器件开发。包含finfet结构的设计,测试条件的制定,器件的tuning包括AC/DC性能提升, 功耗改善, RO速度提升, 可靠性改善. lead team 短期内使器件接近target. 关键MTS标准制定.

1. Core/IO/LDMOS and passive device layout design. Device LDE layout matrix design.

2.Define WAT test condition. Define Vfb,Si and metal Ef, 电阻成分提取,电容成分提取.利用split CV测试mobility.

3. ULVT/LVT/SVT device VT tuning to target by NWF and PWF metal elaborate matrix and implant.

4. Device performance improved by SIP/SiGe doping, proximity and SD anneal. Optimize Fin , Gate CD and profile to improve device performance. RO performance improved to 90%.

6. Solved 1.2/1.5V underdrive IO device SCE by LDD implant tuning.

7. Develop 5V LDMOS to meet device target and improve HCI .

8. Solved N diode LKG high issue and BJT small beta issue.

9. Improve IO device TDDB, HCI.

10. Set up auto WAT data analysis script with JMP and Python.

二:40LP项目器件开发。40LP器件testkey的设计,器件开发,可靠性提高, TCAD仿真等。实现device满足EDR target的要求,32M 0.242um2良率实现高良率,器件可靠性pass。从零建立了有战斗力的TCAD团队。

1. 设计并调试出满足target的HVT device/7V和5V LDMOS/Native device/Poly fuse等.

2. 设计SRAM mismatch, SNM/WM, SRAM CT RC等testkey结构, 并设计更小尺寸的Bitcell结构.

3. 通过优化Cgd0, Cj 改善RingOSC的speed;通过优化SCE,降低RingOSC leakage.

4. 通过优化Cell ratio, 提高SRAM SNM/WM;改善DIBI进而降低SRAM Istdby.

5. 通过改善local variation,优化SRAM mismatch,进而提高read margin和降低Vmin.

6. 解决了IO NMOS和HVT N/PMOS HCI failure issue. and core PMOS NBTI failure issue.

一:19nm DRAM器件开发。管理19nm DRAM CMOS器件团队,包括DDR4和LP DDR4两个 technology的器件开发,并使之满足电路设计和器件可靠性的要求,进入量产。包括从TEG的设计,器件的测试条件定义,电性结果的分析,关键工艺的改进,以及器件window的增大,器件可靠性的提高等。Support array device开发。利用TCAD进行器件开发,协助debug spice model里的异常器件问题。cowork with PDE/QE解决产品良率重大问题和提升可靠性。项目开发的管控,工程师的daily review, Team的培训,团队建设, 新人面试等。

1. CMOS& Passive device TEG design, LO update and GDS&DRC check.

2.建立重要参数如表面态电荷(ICP), 迁移率(Split CV), Cgd(Miller)等的精确量测以及W/L dependence transistor, well isolation,bipolar, gate edge junction,antenna等重要结构的设计和量测。

3.开发JMP脚本使器件分析报告自动化.节约大量数据处理时间.

4. Device development to meet target. Device uniformity improvement including local and global variation.

1) 通过gate CD, offset spacer和main spacer width的matrix 来确定最佳device structure.

2) 优化DPN工艺:改善Nitridation和PNA,降低表面态密度,增大迁移率;避免了在SPA工艺存在的NBTI比较weak的问题。

3) 改善SA device 的mismatch, 降低Avt.

4) 利用dual gate (TiN 和N+poly )来增大平带电压,减少在累积态时的能带弯曲,进而减少array transistor的GIDL.

5) 在Array STI sidewall加入B IMP,抑制pass gate的反型,降低表面势,从而抑制临近device的漏电.

6) 通过在Array node contact生长EPI来降低电阻,通过改变fin height及shape来提高transistor的Ion.

5. Developped Asymmetry transistor,大大改善了HCI. Developped anti-fuse device,降低blow电压的同时提高了blow ratio.

6. 解决产品良率failure issue related to device. 通过nanoprobe,TEM,EFA等找到原因,进而改善工艺提升良率。

7. 解决产品的可靠性的问题。improved thin GOX PMOS的NBTI和IO device的HCI failure issues.

二:HKMG technology development for 15nm DRAM Manage advanced HKMG device development. Lead team to improve HKMG device performance compared to PolySION with metal gate first approach.

1. 优化cap layer 里的dipole 来调节有效功函数,进而得到合适的平带电压和VT.

2. high K 材料中改变Hf的含量获得最佳的EOT和gate leakage. 优化Si含量提高high K的热稳定性。

3. 改善SiGe工艺,调节PMOS work function bias and VT, 增大迁移率。优化SiGe表面态,解决SiGe OX生长速度过快的问题.

4. 改善IL layer工艺,降低表面态,进而降低Tinv, 增大迁移率。

5. 优化DPN工艺,改善NBTI和PBTI.

65nm CIS器件开发。管理CMOS团队,同时协助管理pixel中方团队. 负责65nm CMOS 技术平台的建立及在此基础上开发2000万,1300万像素产品。主要包括重要document的建立,TEG的设计,器件的测试条件定义,器件开发DOE的设计,器件weakpoint的提高和mask reduction等. 利用TCAD进行器件分析和改善,协助Model team对器件重要特性的分析和建模。PDK相关design rule的制定和TEG的设计。工程师的daily review, team的技术培训,新人面试等。

1. GDS Layer mapping table/LO/EDR set up.

2. CMOS, Pixel TEG design and GDS&DRC check.

3. design manual update及其TEG设计验证design rule.

4. SIMS box设计及SIMS data collection.

5. Device development and optimization coworking with TCAD and Spice team including TED suppress,well isolation, Nitrogen doping in DPN, LDD low energy implant improvement and poly inter-diffusion prevention etc.

6. Support pixel device development including PD FWC improvement, white pixel, image lag and blooming improvement, transfer gate saddle design etc.

7. New device DCAP and E-fuse development.

8. Mask reduction to cost down. especially implant mask merge.

一:55nm and 65nm Logic FEOL leader. 历经从technology transfer(from IBM)到产品的成功量产。期间带领group完成FEOL PRS的开发,避免key process weakpoint. Testkey GDS and DRC check. Device development and yield improvement. SRAM SNM margin improvement. 良率和可靠性相关issue的解决等。

1. FEOL PRS criteria的制定,督促和审核module完成的PRS. 确保重要structure AA, GOX, Gate, Spacer和CT满足器件要求。

2. 厚度量测Pad的设计,OCD量测pattern的设计, defect scan策略制定。

3. 通过PWQ和PWORC检查重要layer的weakpoint, 进而提高process window.

4. Device tuning to meet target. Device DOE设计.收集implant 和重要process的sensitivty. 解决重要的device issue, 如Halo在chip的shadow effet, PMOS punch through, slow on-current, reverse NWE. SRAM small SNM, optimize SiN tensile stress to improve NMOS mobility etc.

5. 解决产品良率重大问题。通过EFA,PFA,nanoprobe等查找原因,进而改善相应工艺。如CT ET open, Ni Salicide spike造成的leakage, SRAM中STI的void, ILD中void造成的W bridge等。

6. 解决产品可靠性问题。如IO device HCI和thin GOX的TDDB fail issue. 改善了EM, EFR,HTOL, HAST等问题。

二:65nm Nor Flash team leader. 负责量产产品的CP/RE issue trouble shooting, 重要客户Cypress的技术支持,新产品良率提升以及Product qualification.带领非资深工程师NTO tape out: DRC/JDV check, inline, WAT及其CPK改善.

1. 解决客户产品的slow erase issue, 大大降低了tail bin count.

2. 解决因为Si dislocation造成的retention问题.

3. 解决IMD TDDB fail issue.

4. 完成大容量512M产品的开发,良率提升和产品qualification.

5. Pad crystal defect and Cu out-diffusion improvement.

6. Defect reduction to improve EFR for automotive product.

40nm PRAM(相变存储器)项目研发。主要负责memory cell和40LG的工艺整合和二极管阵列开发。Cell 工艺包括:EPI process(on BNL), AA Loop process, Deep Trench process, HARP process, CT ET process等。器件开发包括:高密度Diode array和相变电阻GST的开发.使diode满足GST相变电阻的驱动需求.同时降低diode array的由于bipolar效应带来的cross talk.

1. As loop process integration owner, define PRS criteria, 督促和审核module完成的PRS. Cowork with module完成工艺开发.

2. Set up process flow and handbook, lot handling, key structure SEM/TEM/EDX analysis.

3. Diode array development. Buried N+ layer(BNL) as WL with DT as isolation. N+ of diode as BL with STI as isolation. Improve diode Ion and improve cross talk.

4. GST resistance development. Improve GST set and reset resistance distribution margin employing material optimization, BEC CD and profile optimization.