My first task was the development of 1.12um pixels. While working on that, I improved on the S5K6A2 for Apple, which through my work is now rated the world’s best performer. I was a Pixel Simulation Leader, directly because of my work on the S5K6A2. My second task was the development of high speed pixel readout circuit for 120fps and above FHD 960fps.
I developed new pixel level simulation bench including analog readout circuit and pixel level transistor model.
My third task was the development of low noise pixel source follower transistor and analog device. I have achieved 28nm analog device in order to improve CFPN characterization and it was patented. Because of this achievement realized not only CIS business using 28nm process node but also high frame rate for analog circuit. And blooming control by sequentially pixel readout method was patented too.
- In order to improve the FWC for the S5K6A2, I again used a new method, which improved performance by 30%, without sacrificing pixel integrity, which had been the problem in the past. This improvement is why the S5K6A2 is considered the world’s best. I received an innovation award from Samsung for my work.
- I developed a new method to improve performance in the S5K2P1 chip. This method raised FWC performance by 20% and lowered Cross-talk by 3%.
- I developed new type 1.12um pixel through developing a new method of PD generation.
- I developed new pixel readout sequence for suppress blooming from PD to FD.
- In order to improve CFPN noise, especially degradation of CFPN using 28nm analog circuits, it was evaluated and find out root cause of CFPN. By this achievement it was able to CIS business of Galaxy S7, S7 note, S8 and expanded Chinese market share.
- I have made FDK(or PDK) evaluation metrics for external foundry selection and also developed the TEG module design methodology. Finally, the correlation of between FDK model and hardware had evaluated and confirmed.
- I developed the custom process and device including layout design rule for analog circuit (such as OTA) to get low power and low noise performance using external foundry. And for external foundry, I set up the noise measurement methodology and surface trap density(Dit) methodology