1、MCU SoC DFT implementation with low pin count design.
2、Co-work with TE on test program developing for ATE.

1、Build 4-member DFT team
2、Design SoC DFT clock structure, DFT control logic and DFT requirement for IP implementation.
3、Build cycle-based DFT pattern (TDL) simulation environment with DV’s support.
4、Compose DFT SDCs for scan shift/capture and MBIST modes, under various test conditions.
5、Build scan insertion and ATPG script/flow with Cadence tools.
6、Co-work with TPE on test program developing for ATE and quality tests.

1、Design clock scheme, DFT control logic for PCIe gen5. Make ATE test plan for PCIe including PHY function test cases. Compose DFT SDC and review timing results.
2、Make the whole solution of hierarchical DFX for a crypto IP, including structural DFT implementation, and DFX features.

1、Build MBIST(SMS) insertion and verification flow at both block and SoC level.
2、Compose DFT SDC for both function and scan shift modes, and supporting SoC level STA.
3、 Integrate PCIe PHY into DFT control network, and make corresponding test scheme.
4、Definition and implementation of SoC JTAG network structure and scan control logic.

Senior Member of Technical Staff (SMTS) ASIC/ Layout Design Engineer, DFT
1、 Lead a 5-member team to implement scan insertion, ATPG, simulation and pattern delivery in multi-projects.
2、DFT infrastructure and clock structure definition of SBIO IPs with multiple power domains.
3、As a project’s DFT lead, control DFT design, MBIST/Scan insertion and ATPG progress, and collaborate with global Front-End, Integration, IP and SoC DFT team

1、Make test plan and the whole structural DFT flow implementation, including MBIST, JTAG, scan insertion, synthesis, simulation, test pattern generation and simulation. And build the whole structural DFT implementation flow.
2、Make test scheme and pattern generation for various 3rd party IPs (including eDRAM, MIPI_DPHY, DDR_PHY, USB_PHY, and etc.) and in-house analog IPs (including PLL, ADC and DAC).
3、Test program development with global test engineers on Verigy 93000. (STATS FastRamp, San Jose; GUC, Hsinchu)
4、RMA analysis; Collaborate with front-end team, analog team, system team, and operation team to improve test coverage.

1、MBIST generation: develop MBIST generation commands and scripts, with memory row redundancy support to improve the memory yield.
2、Memory generation: develop memory automatic generation scripts, support various library and different memory specifications.
3、SystemC design and verification of output controller.

1、Scan chain insertion: learn and develop DFT Compiler command scripts to insert scan chain for chip.
2、Test pattern development (ATPG and functional test patterns like I2C), analysis, and evaluation. Debug and verify test program with test engineers on Teradyne Catalyst in UTAC, Singapore.
3、Implementation, verification and evaluation of TBU (Test Block Unit, a JTAG-based test controller, in charge of test mode control and selection).
4、ADC and PLL module evaluation. Update test pattern of analog modules, and evaluation the performance of them using Vector Generator and Logic Analyzer in lab.
5、Implementation, verification and evaluation of SIO_HI (System Input/Output Host Interface, an I2C-protocol-based and MOVE-architecture-based MCU), and support FAE team for the I2C issue, evaluate I2C interface communication by oscilloscope.
6、Implementation and verification of IQM_AF/SF/AGC (Analog front control / single frequency elimination / analog gain control, in IQ demodulate).
7、Coding style document definition and maintenance; and application note and Data sheet composition and maintenance using FrameMaker.